Programmable logic devices (“PLDs”) are a type of digital IC that a user can program to perform specified logic functions. PLDs typically interface with other ICs in an electronic system, and data is passed between the PLD and other IC(s) through a digital interface.
In high-speed interfaces, a transmitting device (e.g. IC) sends a clock signal to the receiving device (e.g. PLD) with the data. This type of interface is called a “source-synchronous” interface because the data is synchronous with the source's (data transmitter's) clock signal. If the receiver does not adequately route the clock signal to the data loads and meet input setup and hold times, improper data transfer might occur. There are two main types of clocking schemes used for source-synchronous systems, the first is known as a free-running clock scheme, and the second is known as a data strobe scheme.
In a free-running clock scheme, the incoming clock can be phase-shifted to place the clock in the center of the data window using a digital clock manager (“DCM”), which is available on some PLDs. This is particularly useful when targeting large data busses or when there is a training pattern at initialization of the receiving device. More information on using a free-running clock scheme in a PLD is provided in Application Note XAPP609, entitled Local Clocking Resources in Virtex-II™ Devices, available from XILINX, INC., of San Jose, Calif., the disclosure of which is hereby incorporated in its entirety for all purposes.
While DCMs offer fine increments of phase-shifting (commonly referred to as “delay”) of clock signals on the PLD, DCM resources are relatively limited and routing to and from the DCM is relatively restricted. For example, the DCM is typically available only on the clock pin, and it is sometimes desirable to provide phase-shifted clock signals on other pins. Similarly, a DCM might not be at the desired location on the PLD chip. A long electrical path between the DCM and data load can cause additional, potentially variable, clock delay (“clock skew”).
Therefore, techniques for providing phase-shifting of clock signals at a receiving device that overcome the disadvantages of conventional phase-shifting techniques described above are desirable.